Design Verification

Design Verification

  • Prerequisites

    B.E/B.Tech in ECE/EEE, M.E/M.Tech/M.S in VLSI/Embedded Systems/Digital Electronics;

  • Fee

    Rs: 95,000/- Plus 18% GST;

  • No of seats

    30

Admission Test Syllabus:

Need to qualify the screening test and technical interview.Test would be conducted in Basic Electronics – BJT, FET, CMOS; Digital Electronics – Number Systems, Boolean Algebra, K-Maps, Logic Gates, Logic Families, Combinational Circuits, Sequential Circuits and Counters.

Course Content

Fundamental concepts in Digital abstraction, MOSFET switch, CMOS basics, Digital circuit speed, NMOS logic, CMOS logic, combinational logic, sequential logic, synchronous sequential design, timing awareness, setup/hold requirement significance, asynchronous circuits, metastability, synchronization, logic synthesis fundamentals, advanced logic synthesis, Verilog, Verification Flows, Coverage Driven Verification concepts, System Verilog, UVM, Test Bench Components, TLM, Factory Concept, Advantages of UVM flow.

Registration