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ISS Coures

The institute was started with the objective of creating a talent pool of trained Engineers both for in-house requirement and to meet the ever growing demand from other MNCs.

Institute of Silicon Systems Pvt Ltd., (ISS) pioneered an industry leading training program in “VLSI Physical Design” for VDSM Technologies, targeted to industry and individuals using industry standard EDA tools ( Cadence Design Systems www.Cadence.com) . It helped to fill the crucial void of trained manpower in the semiconductor industry which is just taking shape in India.

ISS is managed by professionals with more than 33+ years of rich experience (5 to 8 years of experience in USA) in VLSI industry with an aim of building your career to great heights. Our course curriculum is designed by more than twelve industry experienced professionals. ISS has a track record of more than 80% of the students in VLSI industry.

ISS is centrally located in the heart of the city of Hyderabad, Madhapur and well connected by public transport. Our institute is centralized air-conditioned with corporate ambience of a working office.

ISS is presently offering following full time training programs


VLSI - RTL Verification

ISS is offering world class industry oriented VLSI - RTL Verification training program using Cadence Incisive Enterprise Simulator tool.
Course duration: 16 to 17 weeks.
Time: 9:30 am to 6:30 pm; 5 days a week.
Fee: Rs 75,000 /- (Service tax applicable)
Batch starting on: We will announced in April, 2017.
Entrance exam on: We will announced in April, 2017.
Exam fee: Rs: 200/-

Prerequisites:

B.E/B.Tech in ECE/EEE, M.E/M.Tech/M.S in VLSI/Embedded Systems/Digital Electronics; 2015/2016 - Graduates/Post Graduates with 65% and above aggregate.

Admission Test Syllabus:

Need to qualify the screening test and technical interview.Test would be conducted in Basic Electronics - BJT, FET, CMOS; Digital Electronics - Number Systems, Boolean Algebra, K-Maps, Logic Gates, Logic Families, Combinational Circuits, Sequential Circuits and Counters. (All are subjective type questions)

Course content:

Fundamental concepts in Digital abstraction, MOSFET switch, CMOS basics, Digital circuit speed, NMOS logic, CMOS logic, combinational logic, sequential logic, synchronous sequential design, timing awareness, setup/hold requirement significance, asynchronous circuits, metastability, synchronization, logic synthesis fundamentals, advanced logic synthesis, Verilog, Verification Flows, Coverage Driven Verification concepts, System Verilog, UVM, Test Bench Components, TLM, Factory Concept, Advantages of UVM flow.

VLSI - Custom Layout

ISS is offering world class industry oriented VLSI - Custom Layout training program using Cadence Virtuoso tool.
Course durations: 12 to 14 weeks
Time: 9.30 am to 6.30 pm, 5 days a week.
Fee: Rs: 60,000/- (Service tax applicable)
Batch starting on: We will announce in 3rd week of February.
Entrance exam on. We will announce in 3rd week of February..
Exam fee: Rs: 200/-

Prerequisites:

B.E/B.Tech in ECE/EEE, M.E/M.Tech/M.S in VLSI/Embedded Systems/Digital Electronics; 2016/ 2017- Graduates/Post Graduates with 65% and above aggregate.

Admission Test Syllabus:

Need to qualify the screening test and technical interview.Test would be conducted in Basic Electronics - BJT, FET, CMOS; Digital Electronics - Number Systems, Boolean Algebra, K-Maps, Logic Gates, Logic Families, Combinational Circuits, Sequential Circuits and Counters. (All are subjective type questions)

Course content:

Fundamental concepts in MOSFET fundamentals, Second order effects, Digital logic gates, Fabrication concepts, Latch Up, Analog building blocks, Analog layout concepts like Module based floor plan techniques, Device Matching techniques, Routing techniques (Power, Signal), Shielding concepts, Deep sub-micron process challenges like Well proximity, LOD and STI effects, ESD concepts and Layout guidelines. Physical verification concepts like LVS, DRC and Antenna with Parasitic extraction. Exposure to the Importance of reliability checks like EMIR analysis, DFM checks and ESD path checks. The trainees get to work on 5 to 6 different designs. The assignments are designed in such a way that our trainees have a clear understanding about developing layouts from schematics following the design constraints, process challenges and layout guidelines and verified their designs and extracted within the given specification limits.  

VLSI - Physical Design

ISS is offering world class industry oriented VLSI - Physical Design training program using Cadence Encounter / Innovus.
Course durations: 22 to 24 weeks
Time: 9.30 am to 6.30 pm, 5 days a week.
Fee: Rs: 90,000/- (Service tax applicable)
Batch starting on: We will announced in July, 2017.
Entrance exam on: We will announced in July, 2017
Exam fee: Rs: 200/-

Prerequisites:

B.E/B.Tech in ECE/EEE, M.E/M.Tech/M.S in VLSI/Embedded Systems/Digital Electronics; 2015/2016 - Graduates/Post Graduates with 65% and above aggregate.

Admission Test Syllabus:

Need to qualify the screening test and technical interview.Test would be conducted in Basic Electronics - BJT, FET, CMOS; Digital Electronics - Number Systems, Boolean Algebra, K-Maps, Logic Gates, Logic Families, Combinational Circuits, Sequential Circuits and Counters. (All are subjective type questions)

Course content:

Fundamental concepts in Digital abstraction, Static discipline, MOSFET switch, CMOS basics, Digital circuit speed, NMOS logic, CMOS logic, Combinational logic, Sequential logic, Synchronous sequential design, Timing awareness, Setup/Hold requirement significance, Asynchronous circuits, Metastability, Synchronization, Logic synthesis fundamentals, Advanced logic synthesis (PLE based), Floor planning, Power planning, Placement, Clock tree synthesis, Routing, Signal integrity, IR-drop analysis, OCV analysis, Static timing analysis and advanced Physical design concepts like Low power design techniques. The trainees get to work on 5 to 6 different designs. The assignments are designed in such a way that trainees have a clear understanding about handling the design from Synthesis to Sign-off within the given specification limits of Area, Timing and Power.