Analog layout batch starting on 12th August 2019, entrance exam on July 6, 2019.      Embedded training starting on August 5, 2019 in Pune, entrance exam on June 29, 2019

Design Verification

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VLSI Design-verification

ISS is offering world class industry oriented VLSI - Design Verification training program using Cadence Incisive Enterprise Simulator tool.

VLSI - Physical Design Training

Prerequisites:

B.E/B.Tech in ECE/EEE, M.E/M.Tech/M.S in VLSI/Embedded Systems/Digital Electronics;

Admission Test Syllabus:

Need to qualify the screening test and technical interview.Test would be conducted in Basic Electronics - BJT, FET, CMOS; Digital Electronics - Number Systems, Boolean Algebra, K-Maps, Logic Gates, Logic Families, Combinational Circuits, Sequential Circuits and Counters. (All are subjective type questions)

Course content:

Fundamental concepts in Digital abstraction, MOSFET switch, CMOS basics, Digital circuit speed, NMOS logic, CMOS logic, combinational logic, sequential logic, synchronous sequential design, timing awareness, setup/hold requirement significance, asynchronous circuits, metastability, synchronization, logic synthesis fundamentals, advanced logic synthesis, Verilog, Verification Flows, Coverage Driven Verification concepts, System Verilog, UVM, Test Bench Components, TLM, Factory Concept, Advantages of UVM flow.

VLSI - Design Verification Training

Prerequisites:

B.E/B.Tech in ECE/EEE, M.E/M.Tech/M.S in VLSI/Embedded Systems/Digital Electronics;

Admission Test Syllabus:

Need to qualify the screening test and technical interview.Test would be conducted in Basic Electronics - BJT, FET, CMOS; Digital Electronics - Number Systems, Boolean Algebra, K-Maps, Logic Gates, Logic Families, Combinational Circuits, Sequential Circuits and Counters. (All are subjective type questions)

Course content:

Fundamental concepts in Digital abstraction, MOSFET switch, CMOS basics, Digital circuit speed, NMOS logic, CMOS logic, combinational logic, sequential logic, synchronous sequential design, timing awareness, setup/hold requirement significance, asynchronous circuits, metastability, synchronization, logic synthesis fundamentals, advanced logic synthesis, Verilog, Verification Flows, Coverage Driven Verification concepts, System Verilog, UVM, Test Bench Components, TLM, Factory Concept, Advantages of UVM flow.

VLSI - Analog Layout Training

Prerequisites:

B.E/B.Tech in ECE/EEE, M.E/M.Tech/M.S in VLSI/Embedded Systems/Digital Electronics;

Admission Test Syllabus:

Need to qualify the screening test and technical interview.Test would be conducted in Basic Electronics - BJT, FET, CMOS; Digital Electronics - Number Systems, Boolean Algebra, K-Maps, Logic Gates, Logic Families, Combinational Circuits, Sequential Circuits and Counters. (All are subjective type questions)

Course content:

Fundamental concepts in MOSFET fundamentals, Second order effects, Digital logic gates, Fabrication concepts, Latch Up, Analog building blocks, Analog layout concepts like Module based floor plan techniques, Device Matching techniques, Routing techniques (Power, Signal), Shielding concepts, Deep sub-micron process challenges like Well proximity, LOD and STI effects, ESD concepts and Layout guidelines. Physical verification concepts like LVS, DRC and Antenna with Parasitic extraction. Exposure to the Importance of reliability checks like EMIR analysis, DFM checks and ESD path checks. The trainees get to work on 5 to 6 different designs. The assignments are designed in such a way that our trainees have a clear understanding about developing layouts from schematics following the design constraints, process challenges and layout guidelines and verified their designs and extracted within the given specification limits.

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